This invention relates to semiconductor packaging and, particularly, to flip chip interconnection.
Flip chip packages include a semiconductor die mounted onto a package substrate with the active side of the die facing the substrate. Conventionally, interconnection of circuitry in the die with the substrate is made by way of bumps which are attached to an array of interconnect pads on the die and bonded to a corresponding (complementary) array of interconnect pads (often referred to as “capture pads”) on a patterned metal layer at the die attach surface of the substrate. Typically an underfill between the active side of the die and the die mount surface of the substrate protects the interconnections and mechanically stabilizes the assembly. Underfill materials are known; typically they include a resin, which may be a curable resin, plus a filler, which is typically a fine particulate material (such as, for example, silica or alumina particles). The particular resin and the filler (type of filler material, the particle size(s), e.g.), and the proportion of filler in the resin, are selected to provide suitable properties (mechanical and adhesion) to the underfill material, both during processing and in the resulting underfill. Conventionally the underfill is formed after the interconnection has been made between the interconnect sites on the substrate and the bumps on the die, by applying the underfill material in a liquid form to the narrow space between the die and the substrate near an edge of the die, whereupon the underfill material is permitted to flow by capillary action into the space (“capillary underfill”). Alternatively the underfill can be formed by applying a quantity of underfill material to the active side of the die or to the die mount side of the substrate, then moving the die toward the substrate and pressing the bumps against the interconnect sites (“no-flow underfill”).
Conventionally a flip chip interconnection using a no-flow underfill is made by: dispensing the underfill material onto the substrate, positioning the die onto the substrate (with the bumps on the interconnect sites) using a pick-and-place tool, and heating the assembly to reflow the bumps. Challenges using this conventional method include trapping of filler (which is a component of the underfill material) between the bumps and the metal at the interconnect sites, resulting in an electrically compromised connection; die “float” during reflow, also resulting in poor connection; and formation of voids in the resulting underfill.
Flip chip technology is gaining increasing interest in semiconductor packaging by virtue of compelling advantages in miniaturization and electrical performance over conventional wire bonding technology. However, many entry barriers exist in the areas of infrastructure, manufacturing cost and design.
One major impediment to acceptance of flip chip technology has been an inability to reduce the interconnection pitch. This limitation results primarily from the propensity of adjacent solder bumps to short during the reflow bonding operation.
The areal density of electronic features on integrated circuits has increased enormously, and chips having a greater density of circuit features also may have a greater density of sites for interconnection with a package substrate. Accordingly another impediment to acceptance of flip chip technology has to do with limitations in substrate technology. In conventional flip chip package substrates the capture pads corresponding to the respective solder bumps on the die are relatively large. Additionally, conventional flip chip package substrates include a “solder mask” consisting of a layer of an insulating material over the patterned circuitry on the substrate, having openings formed to expose the capture pads (known as a “solder mask”); the solder mask confines the solder when the bump melts. Techniques for defining the openings have relatively poor resolution, and the design dimensions of the capture pads and additional tolerance dimensions are conventionally provided for the distances between capture pads and adjacent circuitry, to accommodate errors in the positions and sizes of solder mask openings. These two limitations adversely affect the routing efficiency of the substrate to which the die is attached.
The flip chip package, including a die mounted on a substrate, is connected to underlying circuitry, such as a printed circuit board (e.g., a “motherboard”) in the device in which it is employed, by way of second level interconnects (e.g., pins) between the package and the underlying circuit. Another limitation in flip chip substrate technology relates to the fact that the second level interconnects have a significantly greater pitch than the flip chip interconnects, and so the routing on the substrate conventionally “fans out” from the interconnect pads to the second level interconnects. Significant technological advances have enabled construction of fine lines and spaces; but in the conventional arrangement space between adjacent pads limits the number of traces that can escape from the more inward capture pads in the array, and the fan out routing between the capture pads beneath the die and the external pins of the package is conventionally formed on multiple metal layers within the package substrate. For a complex interconnect array, substrates having multiple layers may be required to achieve routing between the die pads and the second level interconnects on the package. Multiple layer substrates are expensive, and in conventional flip chip constructs the substrate alone typically accounts for more than half the package cost (about 60% in some typical instances). The high cost of multilayer substrates has been a factor in limiting proliferation of flip chip technology in mainstream products.
Moreover, in conventional flip chip constructs the escape routing pattern typically introduces additional electrical parasitics, because the routing includes short runs of unshielded circuitry and vias between patterned metal circuit layers in the signal transmission path. Electrical parasitics can significantly limit package performance, particularly at higher frequencies (such as radio frequencies).
A further limitation of conventional flip chip technology is that it requires expensive process apparatus with associated high financial investment levels and manufacturing costs.